Memory systems typically include memory and a memory controller. The memory can comprise a variety of devices such as Single Data Random Access Memory (SD-RAM) or Double Data Rate Random Access Memory (DDR-RAM). The memory is typically packaged as an integrated circuit. The memory controller is typically packaged as another integrated circuit.
The memory and the memory controller are typically connected to each other over a printed circuit board. The memory and memory controller include ball grid arrays. Ball grid arrays are arrays of electrical contacts, known as pins, that are physically accessible by components that are outside of the integrated circuit. The ball grid arrays are soldered to the printed circuit board. Connection paths are etched onto the printed circuit board interconnecting various pins from the memory and the memory controller. The thin small outline package (referred to as TSOP) typically comprises two rows of pins that are arranged on each of the longer side of the device. These rows of pins have a fixed pitch (spacing) between each pin.
The Joint Electron Device Engineering Committee has promulgated standards standardizing the thin small outline packaging (TSOP) pin configuration for synchronous double data rate DRAMs (DDR-SDRAMs). Pursuant to the standard, DDR-SDRAMs are typically rectangular in shape and include a row of pins along two longer sides of the rectangle.
On a multilayer printed circuit board, integrated circuits that are placed on one side of the printed circuit board access other layers of the printed circuit board by what are known as vias. Vias are holes that give access to other layers of the printed circuit board. It is generally preferable to avoid placing access points of adjacent pins too close to each other. Placement of the access points to close to each other can result in interference and crosstalk.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings appended hereto.